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| www..com IP175A LF Preliminary Data Sheet 5 Port 10/100 Ethernet Integrated Switch Features General Description IP175A LF is a low cost 10/100 Ethernet single 5 port 10/100 Ethernet switch with built in chip switch. It integrates a 5-port switch controller, transceivers and memory SSRAM, and 5 10/100 Ethernet transceivers. Build in SSRAM for frame buffer Each of the transceivers complies with the Built in storage of 1K MAC address IEEE802.3, IEEE802.3u, and IEEE802.3x Support flow control - Support IEEE802.3x for flow control for full specifications. The transceivers are designed in duplex mode operation DSP approach with 0.25um technology; they have - Support backpressure for flow control for high noise immunity and robust performance. half duplex mode operation IP175A LF operates in store and forward mode. It 5 port switching fabric - Support two-level hashing algorithm to supports flow control, auto MDI/MDI-X, CoS, port solve MAC address collision base VLAN, and LED functions, etc. Each port can - Support MAC address aging be configured to auto-negotiation or forced - Store and forward mode 10M/100M, full/half duplex, and it is also able to - Broadcast storm protection configure to 100BaseFX transmission mode. - Full line speed capability of 148800 (14880) Using an EEPROM or pull up/down resistors on packets/sec for 100M (10M) specified pins can configure the desired options. - Support 1536 byte data transfer for VLAN IP175A LF does not support "forced 10M half packet traffic mode". - Port base VLAN .com - Port base CoS configuration IP175A LF supports two MII ports for router Integrate 5 ports transceiver application, which supports 4 LAN ports and one - Each port can be auto negotiable or forced WAN port. MII0 is for LAN traffic and MII1 is for 10M/100M, full/half duplex WAN traffic and no external PHY is needed. Both - Each port can be configured as 100BaseFX MII can work in PHY mode and interface to the - Automatic MDI/MDI-X configuration external MAC in this application. The external MAC can monitor or configure IP175A LF by Support two MII, one SMI and extended MII registers for router application accessing MII registers through SMI. Built in regulator for 3.3v to 2.15v MII0 also can be configured to be MAC mode. It is LED status of Link, activity, Full/half duplex, used to interface an external PHY to work as a speed, and power on diagnostic function 4+1 switch. Initial parameter setting by pin or EEPROM (24LC01) configuration Utilize single clock source (25Mhz) 0.25u technology Support Lead Free package (Please refer to the Order Information) DataShee .com Copyright (c) 2004, IC Plus Corp. 1/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet Table Of Contents Features & General Description ........................................................................................................... 1 Table Of Contents................................................................................................................................. 2 Revision History.................................................................................................................................... 2 1 Applications..................................................................................................................................... 3 2 Pin Diagram .................................................................................................................................... 7 3 Pin Descriptions .............................................................................................................................. 8 4 Functional Description .................................................................................................................. 17 4.1 5-port switch application ................................................................................................. 17 4.2 Router application ........................................................................................................... 18 4.3 MII0 MAC mode .............................................................................................................. 19 4.4 MII, SMI and MII register................................................................................................. 20 4.5 Fiber port configuration ................................................................................................... 23 4.6 CoS ................................................................................................................................. 24 4.7 VLAN............................................................................................................................... 25 4.7.1 Port base VLAN ................................................................................................. 25 4.7.2 Tag / un-tag ........................................................................................................ 25 4.8 Initial value set by LED pins............................................................................................ 26 4.9 Built in regulator .............................................................................................................. 27 4.10 Extended MII registers .................................................................................................... 28 4.11 EEPROM register ........................................................................................................... 35 4.12 The basic MII registers.................................................................................................... 46 5 Electrical Characteristics............................................................................................................... 50 5.1 Absolute Maximum Rating .............................................................................................. 50 5.2 DC Characteristic............................................................................................................ 50 .com 5.3 AC Timing........................................................................................................................ 51 5.3.1 Reset Timing ...................................................................................................... 51 5.3.2 MII0 PHY Mode Timing ...................................................................................... 51 5.3.3 MII1 PHY Mode Timing ...................................................................................... 53 5.3.4 MII0 MAC Mode Timing ..................................................................................... 54 5.3.5 SMI Timing ......................................................................................................... 55 5.3.6 EEPROM Timing................................................................................................ 56 6 Order Information.......................................................................................................................... 56 7 Package Detail.............................................................................................................................. 57 t4U.com DataShee Revision History Revision # Change Description IP175A LF-DS-R01 Initial release. IP175A LF-DS-R02 1. Update pin description of REG_OUT on page 14. 2. Add VCC_IO limitation to the operation condition on page 61. 3. Add VCC_IO_1, VCC_IO_2, VCC pin description on page 18 IP175A LF-DS-R03 Update pin description of Reg_out page 14. IP175A LF-DS-R04 Remove MII register 16H. IP175A LF-DS-R05 Remove VLAN from MII Register. IP175A LF-DS-R06 1. ADD AC Timing 2. Change minimum VCC from 2.1v to 2.0v on page 14 & 50 IP175A LF-DS-R07 Add the order information for lead free package. .com Copyright (c) 2004, IC Plus Corp. 2/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet 1 Applications Application 1: IP175A LF 5x Transformer or Fiber MAU 5 port Ethernet switch t4U.com DataShee .com Application 2: MII0 IP175A LF MII1 MAC2 Application 3: MAC1 CPU IP175A LF MII0 4x Transformer or Fiber MAU 1x Transformer ADSL or Cable Modem 4x Transformer or Fiber MAU PHY 4 LAN port + one WAN port (Router) 4 TP ports + one external PHY .com Copyright (c) 2004, IC Plus Corp. 3/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet Applications (continued) Application 1: 5 TP port switch Switch IP175A LF 5 port switch controller PHY 0 PHY 1 PHY 2 PHY 3 PHY 4 Use 5 builtin PHY. MII0 and MII1 ports are not used. 5 TP port t4U.com Application 1: 5 FX port switch Switch DataShee .com IP175A LF Fiber MAU 0 Fiber MAU 1 Fiber MAU 2 Fiber MAU 3 Fiber MAU 4 Use 5 external fiber MAU. MII0 and MII1 ports are not used. 5 FX port .com Copyright (c) 2004, IC Plus Corp. 4/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet Applications (continued) Application 2: 4 LAN port + one WAN port (Router) R o u te r IP 1 7 5 A L F 5 p o rt s w itc h c o n tro lle r (P H Y m o d e M II) M II0 M AC1 CPU PHY 0 PHY 1 PHY 2 PHY 3 PHY 4 M II1 M AC2 4 X L A N p o rt 1 W A N p o rt E th e rn e t PC ADSL or C a b le m o d e m W A N to IS P E th e rn e t t4U.com Application 3: 4 TP port + one external PHY Switch IP175A LF DataShee .com 5 port switch controller (MAC mode MII) MII0 EXT PHY Use 4 builtin PHY (0~3). Use MII0 port to connected the external PHY. PHY 0 PHY 1 PHY 2 PHY 3 PHY 4 4 TP port one external PHY port .com Copyright (c) 2004, IC Plus Corp. 5/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet 2 Pin Diagram LED_SPEED[4] P1_FORCE_FULL LED_SPEED[3] P4_FORCE_FULL LED_FULL[4] P0_FORCE_FULL LED_LINK[4] P2_FORCE_FULL LED_FULL[3] P3_FORCE_FULL LED_SPEED[2] P2_FORCE100 LED_LINK[3] P0_FORCE100 LED_FULL[1] P4_FORCE_100 103 LED_FULL[2] P1_FORCE100 LED_LINK[2] P3_FORCE100 104 REG_OUT RXIM0 RXIP0 GND X2 128 127 126 115 114 VLAN_ON OSCI (X1) FXSD0 GND GND GND GND VCC VCC VCC VCC 112 111 110 125 120 124 123 122 121 119 118 117 116 109 108 107 113 106 105 VCC NC TXOP0 TXOM0 GND VCC GND TXOP1 TXOM1 VCC RXIP1 RXIM1 GND VCC BGRES GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 LED_SPEED[1] BF_STM_EN LED_LINK[1] BK_EN LED_FULL[0] X_EN GND_IO_1 VCC_IO_1 LED_SPEED[0] UPDATE_R4_EN LED_LINK[0] MII0_MAC_MODE GND_SRAM VCC_SRAM RESETB LED_SEL[1] LED_SEL[0] COL0 P0_FORCE MII0_RXCLK RXD0_0 P1_FORCE RXD0_1 P2_FORCE RXD0_2 P3_FORCE RXD0_3 P4_FORCE RXDV0 GND VCC MII0_TXCLK TXD0_0 P0_FORCE TXD0_1 P1_FORCE TXD0_2 P2_FORCE TXD0_3 P3_FORCE TXEN0 P4_FORCE P4MII_SNI P4EXT GND_IO_2 VCC_IO_2 MDC MDIO COL1 MII1_RXCLK RXD1_0 MAC_X_EN RXD1_1 RXD1_2 AGING t4U.com GND RXIP2 RXIM2 VCC TXOP2 TXOM2 GND VCC GND TXOP3 TXOM3 VCC RXIP3 RXIM3 GND GND RXIP4 RXIM4 VCC NC TXOP4 TXOM 4 DataShee IP175A LF .com 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 54 55 56 57 58 59 60 61 62 63 RXDV1 COS_EN FXSD3 VCC TXEN1 TXD1_3 TXD1_2 TXD1_1 FXSD1 TEST1 FXSD2 GND GND VCC SDA VCC .com Copyright (c) 2004, IC Plus Corp. 6/57 RXD1_3 P4_HIGH GND VCC MII1_TXCLK TXD1_0 FXSD4 SCL TEST2 GND GND VCC 64 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet 3 Pin Descriptions Description Input pin Output pin Input pin with internal pull low Input pin with internal pull high Label Type Type IPL1 IPH1 IPL2 IPH2 Description Input pin with internal pull low 22.8k ohm Input pin with internal pull high 22.8k ohm Input pin with internal pull low 92.6k ohm Input pin with internal pull high 113.8k ohm Description Type I O IPL IPH Pin no. LED pins used as initial setting mode during reset 102 BF_STM_EN IPL1 Broadcast storm protection enable 1: enable, 0: disable (default) 101 BK_EN IPH1 Backpressure enable 1: enable (default), 0: disable This pin doesn't set the flow control of MII0 port. MAC_X_EN sets the flow control of MII0 port. 100 t4U.com X_EN IPH1 IEEE802.3X enable 1: enable (default), 0: disable .com This pin doesn't set the flow control of MII0 port. MAC_X_EN sets the flow control of MII0 port. DataShee 97 UPDATE_R4_EN IPL1 Change capability enable A full duplex port will change its capability to half duplex, if the remote full duplex port does not support IEEE802.3x then this function is enabled. It should be pulled low for normal operation. 1: enable, 0: disable (default) .com Copyright (c) 2004, IC Plus Corp. 7/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet Pin Descriptions (continued) Pin no. Label Type Description MII pins used as initial setting mode during reset 113 VLAN_ON IPL VLAN enable 1: enable, 0: disable (default) IP175A LF is separated into 4 VLAN groups if this function is enabled. VLAN 1: port0, port 4; VLAN 2: port 1, port 4; VLAN 3: port 2, port 4; VLAN 4: port 3, port 4; Programming EEPROM registers 0Eh~12h or MII register 13h~15h will overwrite the VLAN configuration. 64 P4_HIGH IPL2 Port4 is set to be high priority port 1: enable, 0: disabled (default) Packets received from port4 are handled as high priority packets if the feature is enabled. Please refer to EEPROM registers 0Eh~12h or MII register 13h~15h for detail information. 63 COS_EN IPL2 Class of service enable .com 1: enable, 0: disabled (default) Packets with high priority tag are handled as high priority packets for all ports if the feature is enabled. Please refer to EEPROM registers 0Eh~12h or MII register 13h~15h for detail information. 65 AGING IPH2 Address aging enable 1: enable, aging time 300s (default), 0: disable t4U.com DataShee .com Copyright (c) 2004, IC Plus Corp. 8/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet Pin Descriptions (continued) Pin no. Label Type IPL Description External MII port enable 1: Both MII interface are enabled for router application. MII1 supports PHY mode only. MII1 interfaces to internal PHY4 of IP175A LF. It is connected to an external MAC device. MII0 supports both PHY mode and MAC mode depending on the setting of MII0_MAC_MOD (pin 96). 0: External MII interface is disabled and IP175A LF works as a 5-port switch (default). 75 P4MII_SNI IPL External MII interface selection 1: SNI interface IP175A LF supports PHY mode SNI (MII0_MAC_MOD=0), i.e., it can be connected to an external MAC. IP175A LF doesn't support MAC mode SNI (MII0_MAC_MOD=1), i.e., it should not be connected to an external PHY. 0: MII interface (default). t4U.com External MII port setting 74 P4EXT DataShee Pin no. Label Type .com Description Flow control enable for external MII0 port 1: enable (default), 0: disable External MII0 port MAC mode 1: MII0 works as a MAC and should be connected to an external PHY. 0: MII0 works as a PHY and should be connected to an external MAC device (default). This pin does not affect MII1 port. External MII0 interface (P4EXT=1) 67 MAC_X_EN IPH2 96 MII0_MAC_MOD IPL1 71, 70 MDC, MDIO IPL SMI The external MAC device uses the interface to program basic and extended MII register to configure PHY 4 and switch controller, .com Copyright (c) 2004, IC Plus Corp. 9/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet Pin Descriptions (continued) Pin no. Label Type Description External MII0 interface (PHY mode, MII0_MAC_MOD=0, P4MII_SNI=0) 81 MII0_TXCLK O MII transmit clock 80, 79, 78, 77 76 TXD0_0, TXD0_1, IPL2 TXD0_2, TXD0_3 TXEN0 IPL2 MII transmit data It is sampled at the rising edge of MII0_TXCLK. MII transmit enable It is used to frame TXD0[3:0]. It is sampled at the rising edge of MII0_TXCLK. 90 COL0 O MII collision It is active when port 4 of switch controller is set to be half duplex and a collision event happens. 84 RXDV0 O MII receive data valid It is used to frame RXD0[3:0]. It is sent out at the falling edge of MII0_TXCLK. 88, 87, 86, 85 t4U.com RXD0_0, RXD0_1, RXD0_2, RXD0_3 MII0_RXCLK O O MII receive data It is sent out at the falling edge of MII0_TXCLK. MII receive clock There is no clock output in this mode. .com 89 DataShee Pin no. Label Type Description External MII0 interface (MAC mode, MII0_MAC_MOD=1, P4MII_SNI=0) 81 MII0_TXCLK I MII transmit clock It is an input clock and it is connected to MII_TXCLK of external PHY. 80, 79, 78, 77 76 TXD0_0, TXD0_1, TXD0_2, TXD0_3 TXEN0 O MII transmit data It is connected to MII_TXD of external PHY. It is sent out at the rising edge of MII0_TXCLK. O MII transmit enable It is an output signal and is connected to MII_TXEN of external PHY. It is sent out at the rising edge of MII0_TXCLK. 90 84 COL0 RXDV0 IPL2 I MII collision It is an input signal and is connected to the MII_COL of external PHY. MII receive data valid It is an input signal and is connected to the MII_RXDV of external PHY. RXDV0 is used to frame RXD0[3:0]. 88, 87, 86, 85 89 .com Copyright (c) 2004, IC Plus Corp. RXD0_0, RXD0_1, RXD0_2, RXD0_3 MII0_RXCLK I Receive data It is NRZ data and is connected MII_RXD[3:0] of external PHY. It is received at the rising edge of MII0_RXCLK. I MII receive clock 10/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet Pin Descriptions (continued) Pin no. Label Type Description External MII1 interface (PHY mode only, P4EXT=1) 62 MII1_TXCLK O MII Transmit clock 61, 60, 59, 58 57 TXD1_0, TXD1_1, IPL2 TXD1_2, TXD1_3 TXEN1 IPL2 MII transmit data It is sampled at the rising edge of MII1_TXCLK. MII transmit enable It is used to frame TXD1[3:0]. It is sampled at the rising edge of MII1_TXCLK. 69 COL1 O MII collision It is active when PHY4 is set to be half duplex and a collision event happens. 63 RXDV1 O MII receive data valid It is used to frame RXD1[3:0]. It is sent out at the falling edge of MII1_RXCLK. MII receive data It is sent out at the falling edge of MII1_RXCLK. 68 MII1_RXCLK O MII .com receive clock t4U.com 67, 66, 65, 64 RXD1_0, RXD1_1, RXD1_2, RXD1_3 O DataShee .com Copyright (c) 2004, IC Plus Corp. 11/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet Pin Descriptions (continued) Pin no. Label Type IPL2 Description Port4 works at force mode. 1: force mode, disable port4 NWAY capability 0: auto-negotiation with all capability enabled (default) It is used to force MII0 port PHY mode if P4EXT is pulled high. It's set by pin 85 if MII0 is in PHY mode and it's set by pin 76 if MII0 is in MAC mode. 86 P3_FORCE IPL2 Port3 works at force mode. 1: force mode, disable port3 NWAY capability 0: auto-negotiation with all capability enabled (default) It's set by pin 86 if MII0 is in PHY mode and it's set by pin 77 if MII0 is in MAC mode. 87 P2_FORCE IPL2 Port2 works at force mode. 1: force mode, disable port2 NWAY capability 0: auto-negotiation with all capability enabled (default) It's set by pin 87 if MII0 is in PHY mode and it's set by pin 78 if MII0 is in MAC mode. .com Port1 works at force mode. 1: force mode, disable port1 NWAY capability 0: auto-negotiation with all capability enabled (default) It's set by pin 88 if MII0 is in PHY mode and it's set by pin 79 if MII0 is in MAC mode. 90 P0_FORCE IPL2 Port0 works at force mode. 1: force mode, disable port0 NWAY capability 0: auto-negotiation with all capability enabled (default) It's set by pin 90 if MII0 is in PHY mode and it's set by pin 80 if MII0 is in MAC mode. Force mode 85 P4_FORCE 76 77 78 t4U.com DataShee 88 P1_FORCE IPL2 79 80 .com Copyright (c) 2004, IC Plus Corp. 12/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet Pin Descriptions (continued) Pin no. Label Type IPL1 Description Force port4 work at 100M or 10M. 1: force 100M 0: force 10M (default) It is used to force MII0 port PHY mode if P4EXT =1. 104 P3_FORCE100 IPL1 Force port3 work at 100M or 10M. 1: force 100M 0: force 10M (default) Force port2 work at 100M or 10M. 1: force 100M 0: force 10M (default) Force port1 work at 100M or 10M. 1: force 100M 0: force 10M (default) Force port0 work at 100M or 10M. 1: force 100M 0: force 10M (default) Force mode 103 P4_FORCE100 105 P2_FORCE100 IPL1 106 P1_FORCE100 IPL1 107 P0_FORCE100 IPL1 t4U.com DataShee Pin no. Label Type .com Description Force mode 108 P4_FORCE_FULL IPL1 Force port4 work at full duplex or half duplex 1: force full duplex 0: force half duplex (default) It is used to force MII0 port PHY mode if P4EXT=1. IP175A LF does not support "force 10M half mode". 109 P3_FORCE_FULL IPL1 110 P2_FORCE_FULL IPL1 Force port3 work at full duplex or half duplex 1: force full duplex 0: force half duplex (default) IP175A LF does not support "force 10M half mode". Force port2 work at full duplex or half duplex 1: force full duplex 0: force half duplex (default) IP175A LF does not support "force 10M half mode". Force port1 work at full duplex or half duplex 1: force full duplex 0: force half duplex (default) IP175A LF does not support "force 10M half mode". Force port0 work at full duplex or half duplex 1: force full duplex 0: force half duplex (default) IP175A LF does not support "force 10M half mode". 111 P1_FORCE_FULL IPL1 112 P0_FORCE_FULL IPL1 .com Copyright (c) 2004, IC Plus Corp. 13/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet Pin Descriptions (continued) Pin no. Label Type I TP receive Description Transceiver 127, RXIP0, RXIM0, 128, RXIP1, RXIM1, 11, 12, RXIP2, RXIM2, 18,19, RXIP3, RXIM3, 29, 30, RXIP4, RXIM4 33, 34 3, 4, 8, 9, 21, 22, 26, 27, 37, 38 TXOP0, TXOM0, TXOP1, TXOM1, TXOP2, TXOM2, TXOP3, TXOM3, TXOP4, TXOM4 BGRES O TP transmit 14 O t4U.com 125, 41, 42, 43, 44 FXSD0~4 I Band gap resister. It is connected to GND through a 6.2 k ohms resistor. Please refer to application circuit for more information. 100Base-FX Signal detect .com IP175A LF will latch the value on FXSDx pins at the end of reset to decide if the port works at 100BaseFX mode. A port works in 100BaseFX mode, if its corresponding signal FXSDx > 0.6v at the end of reset. FXSDx should be connected to GND if the port works in TP mode. That is, a port is a fiber port if its FXSDx is connected to the SD of fiber MAU and a port is a TP port if its FXSDx is connected to GND. DataShee The SD of fiber port is active if the voltage of FXSDx is higher than 1.2v. It is used to inform IP175A LF if the fiber is plugged or not. Pin no. Misc. 123 122 93 120 X1 X2 Label Type I O I O 25M system clock input Crystal pin Reset, low active Regulator output Description RESETB REG_OUT It is used to control external transistor to generate a 2.15v 5% voltage source when VCC_IO_1 and VCC_IO_2 are exactly 3.3v and all ports are link on. To meet the specification of minimum VCC (2.0v), VCC_IO_1 and VCC_IO_2 should be at least 3.3v. The supply current of external transistor used should be at least 1A. .com Copyright (c) 2004, IC Plus Corp. 14/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet Pin Descriptions (continued) Pin no. EEPROM 53 SCL Label Type I/O Description After reset, it is used as clock pin SCL of EEPROM. Its period is longer than 10us. IP175A LF stops reading EEPROM if it finds there is no 55AA pattern in register 0. After reading EEPROM, this pin becomes an input pin. After reset, it is used as data pin SDA of EEPROM. After reading EEPROM, this pin becomes an input pin. 54 SDA IO Pin no. LED 92, 91 Label LED_SEL[1:0] Type IPH Description LED output mode selection. LED_SEL[1:0]=00: LED mode 0, LED_SEL[1:0]=01: LED mode 1, LED_SEL[1:0]=10: LED mode 2, LED_SEL[1:0]=11: LED mode 3 (default) t4U.com 110, 107, 104, 101, 96 LED_LINK[4:0] O Link, Activity (output after reset) LED mode0: 100M Link + Activity (same as mode 2) LED mode1: Receive activity (1: not receiving, flash: receiving) .com LED mode2, 100M Link + Activity (1: 100M Link fail, 0: 100M Link ok and no activity, flash: 100M Link ok and TX/RX activity) LED mode3: Link + Activity (1: link fail, 0: link ok, flash: Link ok and TX/ RX activity) Speed (output after reset) LED mode0: (1: no collision, flash: collision) (note*) LED mode1: (1: speed=10M, 0: speed=100M) LED mode2: Full/half: (1: half, 0: full, flash: collision) LED mode3: (1: speed=10M, 0: speed=100M) Full/half, Link (output after reset) LED mode0, 10M Link + Activity (same as mode 2) LED mode1, Link: (1: Link fail, 0: Link ok) LED mode2, 10M Link + Activity (1: 10M Link fail, 0: 10M Link ok and no activity, flash: 10M Link ok and TX/RX activity) LED mode3: Full/half: (1: half, 0: full, flash: collision) DataShee 111, 108, 105, 102, 97 112, 109, 106, 103, 100 LED_SPEED[4:0] O LED_FULL[4:0] O Note: LED_SPEED[0] shows collision information for all ports. LED_SPEED[4:1] is undefined. .com Copyright (c) 2004, IC Plus Corp. 15/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet Pin Descriptions (continued) Pin no. Power 98, 72 Label VCC_IO_1, VCC_IO_2 Type I Description Power for output pins They should be connected 3.3v if MII, EEPROM, or built in regulator (REG_OUT) is used. They can be connected to the same power source as VCC if IP175A LF works as a 5-port switch without using bulilt in regulator. Power for core 2.15v~2.625v VCC I Pin no. Label Type IPL Description Test mode selection They should be connected to GND for normal operation. Test mode 51, 52 TEST1, TEST2 t4U.com DataShee .com .com Copyright (c) 2004, IC Plus Corp. 16/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet 4 4.1 Functional Description 5-port switch application IP175A LF works as a 5 TP port auto MDI-MDIX switch when all fibers and MII function are disabled. In this case, both FXSDx and P4EXT should be pulled low. Each port can be with auto-negotiation or force mode in this application. An example to illustrate the configuration setting of port4 when P4EXT is pulled low and MII is disabled Port 4 4 4 4 4 4 TP V V V V --FX ----V V Nway V V -V --Capability All capability 10M/ full 100M/ half 100M/ full 100M half 100M full FXSD4 0 0 0 0 > 0.6v > 0.6v P4_FORCE P4_FORCE100 P4_FORCE_FULL 0 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 Note: 1. The configuration not in the table is inhibited. 2. "--": Not applicable t4U.com IP 1 7 5 A L F s w itc h c o n tro lle r .com p o rt 1 p o rt 2 p o rt 3 PHY 1 PHY 2 PHY 3 DataShee p o rt 0 PHY 0 p o rt 4 PHY 4 .com Copyright (c) 2004, IC Plus Corp. 17/57 July 12, 2005 IP175A LF-DS-R07 DataSheet4 U .com www..com IP175A LF Preliminary Data Sheet 4.2 Router application IP175A LF supports two MII ports, MII0 and MII1, for router application when P4EXT is pulled high. Pin P4_FORCE, P4_FORCE100 and P4_FORCE_FULL decide the speed and duplex of MII0. The speed and duplex of MII1 depend on the result of auto-negotiation of PHY4. But, programming basic MII registers through SMI can modify them. MAC_X_EN pin decides the flow control option of MII0. It is illustrated in the following table. MII0 P4EXT MAC_X_EN P4_FORCE P4_FORCE100 P4_FORCE_FULL 0 1 1 1 1 1 1 1 X: "don't care" t4U.com Speed X 0 0 0 0 1 1 1 X 1 1 1 1 1 1 1 X 1 1 0 0 1 1 0 X 1 0 1 0 1 0 1 Flow control MII0 disabled. 100M Full Off 100M Half Off 10M Full Off 10M Half Off 100M Full On 100M Half On 10M Full On Duplex IP175A LF can work as a router with 4 LAN ports and one WAN port, which use internal PHY (PHY4). MII0 is the interface between port4 of internal switch controller and external MAC. MII1 is the interface .com between internal transceiver PHY4 and external MAC. The switch controller forwards frames from port0~3 to MII0 and vice versa. PHY4 works as an independent single PHY for external MAC. MII0 works at PHY mode in this application (MII_MAC_MOD=0). IP 1 7 5 A L F s w itc h c o n tro lle r p o rt 0 PHY 0 p o rt 1 PHY 1 p o rt 2 PHY 2 p o rt 4 p o rt 3 CPU PHY 3 PHY 4 M II1 (W A N ) MAC DataShee (P H Y m o d e ) M II0 (L A N ) MAC L A N p o rt W A N p o rt .com Copyright (c) 2004, IC Plus Corp. 18/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet 4.3 MII0 MAC mode MII0 works at MAC mode if MII_MAC_MOD is pulled high. MII0 is an interface between port4 of internal switch controller and external PHY. It replaces an Ethernet PHY with a user specified PHY in this application. The speed and duplex of MII0 are configured by P4_FORCE, P4_FORCE100 and P4_FORCE_FULL. IP175A LF doesn't read the status of external PHY via SMI at this mode. IP 1 7 5 A L F s w itc h c o n tr o lle r p o rt 0 PHY 0 p o rt 1 PHY 1 p o rt 2 PHY 2 p o rt 4 p o rt 3 PHY 3 PHY 4 (u n u s e d ) (M A C m o d e ) M II0 PHY t4U.com DataShee .com .com Copyright (c) 2004, IC Plus Corp. 19/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet 4.4 MII, SMI and MII register IP175A LF supports two MII and one SMI (MDC and MDIO). Two MII interface to the external MAC for data transfer and the SMI is used to program switch controller and PHY4. IP175A LF provides basic MII registers for PHY4 and extended MII registers for switch controller. The external MAC monitors or configures PHY4 by reading or writing the basic MII registers through SMI. The external MAC monitors or configures switch controller by reading or writing the extended MII registers through SMI. The switch controller can be configured by pin and EEPROM, too. The operation is illustrated in the following diagrams. in it ia l v a u le f r o m p in s IP 1 7 5 A L F EEPROM r e g is t e r s S w it c h c o n t r o lle r E x te n d e d M II r e g is t e r s M D C , M D IO MAC EEPROM SCL, SDA CPU MAC t4U.com PHY 4 DataShee .com r e g is t e r s B a s ic M I I T h r e e w a y s t o c o n f ig u r e I P 1 7 5 A , b y p in s , E E P R O M , o r p r o g r a m m in g M I I r e g is t e r s .com Copyright (c) 2004, IC Plus Corp. 20/57 July 12, 2005 IP175A LF-DS-R07 DataSheet4 U .com www..com IP175A LF Preliminary Data Sheet Parameter setting with pins, EEPROM and MII registers in IP175A LF Read default setting on pins at the end of reset EEPROM exists ? yes Update the default setting by reading EEPROM no Enable MII registers ? no t4U.com yes .com Change the setting by programming SMI DataShee Done .com Copyright (c) 2004, IC Plus Corp. 21/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet Serial management interface (SMI) User can access IP175A LF's MII registers through serial management interface with pin MDC and MDIO. A specific pattern on MDIO is used to access a MII register. Its format is shown in the following table. When the SMI is idle, MDIO is in high impedance. To initialize the MDIO interface, the management entity sends a sequence of 32 contiguous "1" and "start" on MDIO. S yatem diagram 175A LF MDC MDI O CPU Frame format Read Operation Write Operation t4U.com MDC z DataShee .com z MDIO 1..1 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 1..1 idle start code write op A A A A A R R R R R TA b b b b b b b b b b b b b b b b 1111119876543210 4321043210 PHY address = Reg address = 543210 Register data 01h 00h idle MDC MDIO z z z 1..1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 Z 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1..1 idle start code read op A A A A A R R R R R TA b b b b b b b b b b b b b b b b 1111119876543210 4321043210 PHY address = Reg address = 543210 Register data 01h 00h idle .com Copyright (c) 2004, IC Plus Corp. 22/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet 4.5 Fiber port configuration Each port of IP175A LF can be configured to be a fiber port or a TP port. A port becomes a fiber port if its FXSDx is connected to a fiber MAU or it is pulled high. A port becomes a TP port if its FXSDx is pulled low. It is illustrated in the following table. Port configuration Fiber port Fiber signal detect --V Off V On Voltage on FXSDx < 0.6v > 0.6v, < 1.2v > 1.2v TP port V --- Condition -Fiber unplugged Fiber plugged The following is an example that IP175A LF is configured to be 3 TP ports and 2 fiber ports. In this case, the speed and duplex of fiber ports are defined by pin P0_FORCE100, P0_FORCE_FULL, P1_FORCE100, and P1_FORCE_FULL. VCC IP175A LF VCC Fiber MAU t4U.com FXSD0 .com FXSD1 DataShee Fiber MAU FXSD4 FXSD3 FXSD2 .com Copyright (c) 2004, IC Plus Corp. 23/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet 4.6 CoS IP175A LF supports two type of Cos. One is port base priority function and the other is frame base priority function. IP175A LF supports two levels of priority queues. A high priority packet will be queued in the memory as a high priority queue, this action will ensure more bandwidth for the high priority packets in the transmission. The packets received from high priority port will be handled as high priority frames if the port base priority is enabled. It is enabled by programming the corresponding bit in EEPROM register 0Eh~12h of or MII register 13h~15h. Each port of IP175A LF can be configured as a high priority port individually. IP175A LF examines the specific bits of VLAN tag and TCP/IP TOS for priority frames if the frame base priority is enabled. The packets will be handled as high priority frames if the value of VLAN tag or TCP/IP TOS field meets the high priority requirement. It is enabled by programming the corresponding bit in EEPROM register 16H~21H or MII register 17h~1Ch. The frame base priority function of each port can be enabled individually. The Cos function can be active even if there is no EEPROM. IP175A LF supports an easy way to enable a sub set CoS function without EEPROM. Port 4 can be set as a high priority port if pin 64 (p4_high) is pulled high. Frame base priority function of all ports is enabled if pin 63 (Cos_en) is pulled high. The setting in register takes precedence of the setting on pins. t4U.com DataShee .com .com Copyright (c) 2004, IC Plus Corp. 24/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet 4.7 4.7.1 VLAN Port base VLAN IP175A LF supports port base VLAN functions. It separates IP175A LF into some groups (VLAN). A port is limited to communicate with other ports within the same group when the function is enabled. Frames are limited in a VLAN group and will not transmit out of this VLAN group. A port can be assigned to one or more VLAN groups. The members (ports) of a VLAN group are assigned by programming EEPROM register 0Eh~12h of or MII register 13h~15h. The VLAN function can be active even if there is no EEPROM. IP175A LF supports an easy way to enable a sub set VLAN function without EEPROM. A default configuration of VLAN is adopted if pin 113 (VLAN_on) is pulled high. The VLAN group in this mode is illustrated in the pin description of VLAN_on. It is benefit in a router application that an individual LAN port can shares a WAN port. The setting in register takes precedence of the setting on pins. 4.7.2 Tag / un-tag IP175A LF supports tag / un-tag functions. When the function is enabled, IP175A LF inserts the pre-defined tag into a forwarded frame if the frame is forwarded to a tagged field. IP175A LF strips the tag of a frame if the frame is forwarded to an untagged field. The operation is illustrated as follows. IP175A LF doesn't support tag VLAN function. Frame type of the received packet Untagged The operation of a output port Forward to a untagged filed Forward to a tagged field Transmit as received 1. Insert VLAN tag to the packet. .com The inserted VLAN tag is defined in the 2. EEPROM register of source port. Strip tag 1. Keep priority field. 2. Modify the VLAN ID. 3. The modified VLAN tag is defined in the EEPROM register of source port. Strip tag Transmit as received t4U.com DataShee Priority-tagged (VLAN ID=0) VLAN-tagged .com Copyright (c) 2004, IC Plus Corp. 25/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet 4.8 Initial value set by LED pins Most configuration pins are shared with LED pin in IP175A LF. These multi-function pins are input during reset period and are LED output after reset. IP175A LF reads initial value via pins during the reset period. An initial value is set to 1 (0) by connecting a pin to vcc (gnd) through a 10k (1k) resistor as shown on the following figure. The application circuit is shown below. VCC VCC VCC LED pin 220 1k LED pin 220 1k to set initial value = 1 with pull up 1k ohm resister to VCC t4U.com to set initial value = 0 with pull down 1k ohm resister to GND DataShee .com VCC LED pin 220 to use default value (use no resistor to leave it open) .com Copyright (c) 2004, IC Plus Corp. 26/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet 4.9 Built in regulator IP175A LF built in a linear regulator to generate 2.15v power. The applications are shown below. VCC = 3.6v (from adaptor) (generated 2.15v ) R 3.3v VCC_IO_1 VCC_IO_2 linear regulator REG_OUT VCC IP175A LF Pure switch with a 3.6v power adaptor. VCC = 3.3v (from board ) generated 2.15v VCC_IO_1 REGOUT VCC t4U.com VCC_IO_2 linear .com regulator IP175A LF Router with an on board 3.3v power source DataShee VCC (from board) VCC VCC_IO_1 VCC_IO_2 internal regulator is not used IP175A LF linear regulator Pure switch uses on board single power source .com Copyright (c) 2004, IC Plus Corp. 27/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet 4.10 MII Extended MII registers ROM Function R/W Description Default MII register 12H (18D) 12.15 2.1 LED_SEL [1:0] 12.14 2.0 12.13 4.7 X_EN 12.12 4.4 BK_EN 12.11 4.2 BF_STM_EN t4U.com 12.10 4.3 MAC_X_EN 12.7 -- MII_REGISTER_ EN Led_sel, LED mode selection. LED_SEL[1:0]=2'b00: LED mode 0, LED_SEL[1:0]=2'b01: LED mode 1, LED_SEL[1:0]=2'b10: LED mode 2, LED_SEL[1:0]=2'b11: LED mode 3 (default) R/W X_en, IEEE 802.3x flow control enable This signal is used as pause_en for digital parts. 1: enable, 0:disable R/W Bk_en, Backpressure enable 1: enable, 0: disable R/W Broadcast storm enable 1: enable Drop the incoming packet if the number of queued broadcast packet is over the threshold. The threshold is defined in register 0AH[14:13]. 0: disable R/W MII0 flow control enable .com 1: enable, 0: disable R/W 1: select MII register 0: select EEPROM register This bit should not be enabled until the contents of MII registers are all filled with correct value. Update_r4_en, Change capability enable A full duplex port will change its capability to half duplex, if the remote full duplex port does not support 802.3x and this function is enable. 1: enable, 0: disable Aging time, Aging time of address table selection An address tag in hashing table will be dropped if this function is turned on and its aging timer expires. Aging =bit[4] 0: no aging 1: aging time 300sec (default) Speed of MII0 1: 100M 0: 10M It is speed of MII0 if P4_EXT is enabled. It is speed of port4 if P4EXT is disabled R/W 2'b11 1 1 0 DataShee 1 0 12.6 B.4 UPDATE_R4_EN R/W 0 12.4 12.3 6.5 6.4 Reserved AGING R/W R/W 0 1 12.2 -- MII0_SPEED RO 0 .com Copyright (c) 2004, IC Plus Corp. 28/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet MII ROM Function R/W Description Default MII register 12H (18D) 12.1 -MII0_FDX RO Speed of MII0 1: full duplex 0: half duplex It is duplex of MII0 if P4_EXT is enabled. It is duplex of port4 if P4EXT is disabled 0 12.0 6.6 Reserved R/W 0 MII ROM Function R/W Description Default MII register 13H (19D) 13.15 -- 13.14 E.6 P0_COS 13.13 E.5 P0_HIGH t4U.com 13.12 -- Reserved R/W Don't care R/W Port0 Class of service enable 1: enable, 0: disabled (default) Packets with high priority tag from port0 are handled as high priority packets. R/W Port0 set to be high priority port 1: enable, 0: disabled (default) Packets received from port0 are handled as high priority packets. Don't care .com 0 0 0 DataShee 13.7 13.6 F.6 P1_COS R/W 13.5 F.5 P1_ HIGH R/W 13.4 -- Reserved Port1 Class of service enable 1: enable, 0: disabled (default) Packets with high priority tag from port1 are handled as high priority packets. Port1 set to be high priority port 1: enable, 0: disabled (default) Packets received from port1 are handled as high priority packets. Don't care 0 0 13.0 MII ROM Function R/W Description Default MII register 14H (20D) 14.15 -14.14 10.6 P2_COS 14.13 10.5 P2_ HIGH R/W Don't care R/W Port2 Class of service enable 1: enable, 0: disabled (default) Packets with high priority tag from port2 are handled as high priority packets. R/W Port2 set to be high priority port 1: enable, 0: disabled (default) Packets received from port2 are handled as high priority packets. 29/57 0 0 0 .com Copyright (c) 2004, IC Plus Corp. July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet MII ROM Function R/W Description Default MII register 14H (20D) -Reserved 14.12 Don't care 14.7 14.6 11.6 P3_COS R/W 14.5 11.5 P3_ HIGH R/W 14.4 -- Reserved Port3 Class of service enable 1: enable, 0: disabled (default) Packets with high priority tag from port3 are handled as high priority packets. Port3 set to be high priority port 1: enable, 0: disabled (default) Packets received from port3 are handled as high priority packets. Don't care 0 0 14.0 MII t4U.com ROM Function R/W Description Default MII register 15H (21D) 15.15 -- 15.14 12.6 P4_COS 15.13 12.5 P4_ HIGH 15.12 -- Reserved R/W Don't care R/W Port4 Class of service enable 1: enable, 0: disabled (default) .com Packets with high priority tag from port4 are handled as high priority packets. R/W Port4 set to be high priority port 1: enable, 0: disabled (default) Packets received from port4 are handled as high priority packets. Don't care 0 0 DataShee 0 15.0 MII ROM Function R/W Description Default MII register 16H (22D) is reserved -13.4 P4_FORCE R/W -- 13.3 P3_FORCE R/W -- 13.2 P2_FORCE R/W -- 13.1 P1_FORCE R/W Port4 force mode enable 1: enable force mode 0: disable force mode, port4 NWAY with all capability Port3 force mode enable 1: enable force mode 0: disable force mode, port3 NWAY with all capability Port2 force mode enable 1: enable force mode 0: disable force mode, port2 NWAY with all capability Port1 force mode enable 1: enable force mode 0: disable force mode, port1 NWAY with all capability 30/57 0 0 0 0 .com Copyright (c) 2004, IC Plus Corp. July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet MII ROM Function R/W Description Default MII register 16H (22D) is reserved -13.0 P0_FORCE R/W -- 14.4 P4_FORCE100 R/W -- 14.3 P3_FORCE100 R/W -- 14.2 P2_FORCE100 R/W -- 14.1 P1_FORCE100 R/W t4U.com -- 14.0 P0_FORCE100 R/W -- 15.4 P4_FORCE_FULL R/W -- 15.3 P3_FORCE_FULL R/W -- 15.2 P2_FORCE_FULL R/W -- 15.1 P1_FORCE_FULL R/W -- 15.0 P0_FORCE_FULL R/W 16.0 -- Port0 force mode enable 1: enable force mode 0: disable force mode, port0 NWAY with all capability Force port4 to be 100M 1: force to be 100M 0: force to be 10M It is valid only if p4_force (15h[15]) is set to 1'b1. Force port3 to be 100M 1: force to be 100M 0: force to be 10M It is valid only if p3_force (15h[14]) is set to 1'b1. Force port2 to be 100M 1: force to be 100M 0: force to be 10M It is valid only if p2_force (15h[13]) is set to 1'b1. Force port1 to be 100M 1: force to be 100M 0: force to be 10M It is valid only if p1_force (15h[12]) is set to 1'b1. Force port0 to be 100M 1: force to be 100M 0: force to be 10M .com It is valid only if p0_force (15h[11]) is set to 1'b1. Force port4 to be full duplex 1: force full duplex 0: force half duplex It is valid only if p4_force (15.15) is set to 1'b1. Force port3 to be full duplex 1: force full duplex 0: force half duplex It is valid only if p4_force (15.14) is set to 1'b1. Force port2 to be full duplex 1: force full duplex 0: force half duplex It is valid only if p4_force (15.13) is set to 1'b1. Force port1 to be full duplex 1: force full duplex 0: force half duplex It is valid only if p4_force (15.12) is set to 1'b1. Force port0 to be full duplex 1: force full duplex 0: force half duplex It is valid only if p4_force (15.11) is set to 1'b1. Reserved 0 0 0 0 0 0 DataShee 0 0 0 0 0 .com Copyright (c) 2004, IC Plus Corp. 31/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet MII ROM Function R/W Description Default MII register 17H (23D) 17[15:11] 16[4:0] Add VLAN tag R/W Add VLAN tag 17H[11] 1: port0 adds a VLAN tag to each outgoing packet. 0: port0 doesn't add a VLAN tag. 17H[12] 1: port1 adds a VLAN tag to each outgoing packet. 0: port1 doesn't add a VLAN tag. 17H[13] 1: port2 adds a VLAN tag to each outgoing packet. 0: port2 doesn't add a VLAN tag. 17H[14] 1: port3 adds a VLAN tag to each outgoing packet. 0: port3 doesn't add a VLAN tag. 17H[15] 1: port4 adds a VLAN tag to each outgoing packet. 0: port4 doesn't add a VLAN tag. Remove VLAN tag 17H[6] .com 1: port0 removes the VLAN tag from each outgoing packet. 0: port0 doesn't remove the VLAN tag. 17H[7] 1: port1 removes the VLAN tag from each outgoing packet. 0: port1 doesn't remove the VLAN tag. 17H[8] 1: port2 removes the VLAN tag from each outgoing packet. 0: port2 doesn't remove the VLAN tag. 17H[9] 1: port3 removes the VLAN tag from each outgoing packet. 0: port3 doesn't remove the VLAN tag. 17H[10] 1: port4 removes the VLAN tag from each outgoing packet. 0: port4 doesn't remove the VLAN tag. 5'b0 t4U.com 17[10:6] 17[4:0] Remove VLAN tag R/W 5'b0 DataShee .com Copyright (c) 2004, IC Plus Corp. 32/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet MII ROM Function R/W Description Default MII register 18H (24D) 18[15:8] 19[7:0] Port 0 vlan_tag[15:8] R/W R/W 18[7:0] 18[7:0] Port 0 vlan_tag[7:0] Vlan_tag_0_high This register defines the high byte of VLAN tag for port 0. Vlan_tag_0_low This register defines the low byte of VLAN tag for port 0. 8'b0 8'b0 MII ROM Function R/W Description Default MII register 19H (25D) 19[15:8] 1B[7:0] Port 1 vlan_tag[15:8] 19[7:0] 1A[7:0] Port 1 vlan_tag[7:0] R/W R/W Vlan_tag_1_high This register defines the high byte of VLAN tag for port 1. Vlan_tag_1_low This register defines the low byte of VLAN tag for port 1. 8'b0 8'b0 MII ROM Function R/W Description Default t4U.com MII register 1AH (26D) 1A[15:8] 1D[7:0] Port 2 vlan_tag[15:8] R/W R/W 1A[7:0] 1C[7:0] Port 2 vlan_tag[7:0] Vlan_tag_2_high This register defines the high byte of VLAN tag for port 2. Vlan_tag_2_low .com This register defines the low byte of VLAN tag for port 2. 8'b0 8'b0 DataShee MII ROM Function R/W Description Default MII register 1BH (27D) 1B[15:8] 1F[7:0] Port 3 vlan_tag[15:8] R/W R/W 1B[7:0] 1E[7:0] Port 3 vlan_tag[7:0] Vlan_tag_3_high This register defines the high byte of VLAN tag for port 3. Vlan_tag_3_low This register defines the low byte of VLAN tag for port 3. 8'b0 8'b0 MII ROM Function R/W Description Default MII register 1CH (28D) 1C[15:8] 21[7:0] Port 4 vlan_tag[15:8] 1C[7:0] 20[7:0] Port 4 vlan_tag[7:0] R/W R/W Vlan_tag_4_high This register defines the high byte of VLAN tag for port 4. Vlan_tag_4_low This register defines the low byte of VLAN tag for port 4. 8'b0 8'b0 .com Copyright (c) 2004, IC Plus Corp. 33/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet MII ROM Function R/W Description Default MII register 1DH (29D) 1D[15:12] -1D.11 -Reserved 1D.10 -- jab_on 1D.9 -- heartbt_en, 1D.8 -- reptr_en 1D.7 -- lp_nway_able 1D.6 -- polrev t4U.com 1D.5 -- phyaddr_fix 1D[4:0] -- phyaddr Jabber enabled. 1: jabber function enabled 0: jabber function disabled R/W Heartbeat enabled. 1: heartbeat function enabled 0: heartbeat function disabled R/W Select NIC or repeater mode. 1: repeater mode 0: NIC mode RO Link partner is auto-negotiation able. 1: link partner supports auto-negotiation 0: link partner doesn't support auto-negotiation RO Analog transmit/receive signal polarity 1: RX+- polarity reversed 0: RX+- polarity not reversed R/W PHY address fix or not. 1: MII registers can be accessed only if the PHY address filed in management frame matches the .com content of MII register 29[4:0]. 0: MII registers can be accessed in spite of the PHY address. R/W Define PHY address RO RO R/W Reserved 0 1 0 0 1 0 0 0 DataShee 5'b0 .com Copyright (c) 2004, IC Plus Corp. 34/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet 4.11 EEPROM register Description Default ROM MII Pin name EEPROM registers 00~01H 0[7:0] --1[7:0] EEPROM enable register This register should be filled with 55AA. IP175A LF will check the specified pattern to confirm a valid EEPROM exists. The initial setting is updated after power on reset only if the specified pattern 55AA is found. AA 55 ROM MII Pin name Description (LED output selection register) Default EEPROM registers 02H 2[7:2] --2[1:0] 12[15:14] LED_SEL[1:0] Reserved Led_sel, LED mode selection. LED_SEL[1:0]=00: LED mode 0, LED_SEL[1:0]=01: LED mode 1, LED_SEL[1:0]=10: LED mode 2, LED_SEL[1:0]=11: LED mode 3 (default) Please refer to pin description for detail LED definition. .com Description 6'b0 11 t4U.com DataShee ROM MII Pin name EEPROM registers 03H 3[7:0] --- Default Reserved 8'b0 ROM MII Pin name Description (Switch control register 1) Default EEPROM registers 04H 4.7 12.13 X_en (LED_FULL[0]) 4[6:5] --4.4 12.12 Bk_en (LED_LINK[1]) 4.3 12.10 Mac_x_en (RXD1_0) 12.11 Bf_stm_en (LED_SPEED[1]) 4.2 X_en, IEEE 802.3x flow control enable This signal is used as pause_en for digital parts. 1: enable, 0:disable Reserved Bk_en, Backpressure enable 1: enable, 0: disable Mac_x_en, External Mac port flow control enable 1: enable, 0:disable Broadcast storm enable 1: enable Drop the incoming packet if the number of queued broadcast packet is over the threshold. The threshold is defined in register 0AH[14:13]. 0: disable 35/57 1 2'b0 1 1 0 .com Copyright (c) 2004, IC Plus Corp. July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet ROM MII Pin name Description (Switch control register 1) Default EEPROM registers 04H 4.1 Reserved 4.0 Reserved 0 1 ROM MII Pin name Description (Switch control register 2) Default EEPROM registers 05H 5[7:6] --5.5 --5[4:3] --- 5[2:0] -- -- Reserved Reserved Bp_kind, Backpressure type selection It is valid only if Bk_en (02H[4]) is set to 1'b1. 00: carrier base backpressure 01: collision base backpressure with hashing 10: collision base backpressure without hashing Reserved 2'b0 1'b0 00 3'b0 t4U.com ROM MII Pin name EEPROM registers 06H 6.7 --- Description (Switch control register 3) .com Default DataShee No drop16, A port will drop the transmitting packet after 16 consecutive collisions if this function is turned on. 1: do not drop, 0: drop 1 6.6 6.5 6.4 12.0 -12.4 -12.3 Aging (RXD1_2) Agetime, Aging time of address table selection An address tag in hashing table will be dropped if this function is turned on and its aging timer expires. Aging =bit[4] 0: no aging 1: aging time 300sec (default) Twopart, Turn on twopartD IP175A LF examine the carrier idle for 64 bits only when it is back off if this function is turned. 1: turn on, 0: turn off Modbck, Turn on modified back off algorithm The maximum back off period is limited to 16-slot time if this function is turned on. 1: turn on (default), 0: turn off Reserved 36/57 0 0 1 6.2 -- -- 1 6.1 -- -- 1 6.0 .com -- -- 0 Copyright (c) 2004, IC Plus Corp. July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet ROM MII Pin name EEPROM registers 07H 7[7:0] --Description Default Reserved Description (Transceiver control register 1) 8'b0 ROM MII Pin name Default EEPROM registers 08H 8[7:0] --- Reserved Description (Transceiver control register 2) 8'b0 ROM MII Pin name Default EEPROM registers 09H 9[7:2] --9.1 --- Reserved Savepw_a_en, Save power mode Digital sends wake up signal to analog before sending FLP if this function is active. 0: disable, 1: enable The default value must be adopted for normal operation. MDI/MDI-X enable 1: enable (default), 0:disable .com This function should be tuned on for normal operation. Disable MDIX is inhibited. Description (Transceiver verification register 1) 6'b0 1 t4U.com 9.0 -- -- 1 DataShee ROM MII Pin name Default EEPROM registers 0AH A[7:6] --A.5 --A.4 --A.3 --A.1 --A.0 --- Reserved Reserved Reserved Reserved Reserved Reserved 00 0 0 0 0 0 ROM MII Pin name Description (Transceiver verification register 2) Default EEPROM registers 0BH B.7 --B.6 --B.5 --- Reserved Reserved Reserved 1'b0 1'b0 0 .com Copyright (c) 2004, IC Plus Corp. 37/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet ROM MII Pin name Description (Transceiver verification register 2) Default EEPROM registers 0BH B.4 12.6 Update_r4_en (LED_SPEED[0]) B.3 B.2 B.1 B.0 ----- ----- Update_r4_en, Change capability enable A full duplex port will change its capability to half duplex, if the remote full duplex port does not support 802.3x and this function is enable. 1: enable, 0: disable Reserved Reserved Reserved Reserved 0 0 0 0 0 ROM MII Pin name Description (Testing & verify mode register 1) Default t4U.com EEPROM registers 0CH C.7 --C.6 --C[5:0] --- Reserved Reserved Reserved .com Description (Testing & verify mode register 2) 0 0 6'b0 DataShee ROM MII Pin name Default EEPROM registers 0DH D[7:3] --D.2 --D.1 --D.0 --D.0 --- Reserved Reserved Reserved Reserved Reserved 0 1 0 0 1 ROM MII Pin name Description (VLAN register 0) Default EEPROM registers 0EH E.7 --E.6 13.14 -- E.5 13.13 -- Don't care Port0 Class of service enable 1: enable, 0: disabled (default) Packets with high priority tag from port0 are handled as high priority packets. Port0 set to be high priority port 1: enable, 0: disabled (default) Packets received from port0 are handled as high priority packets. 1'b0 1'b0 .com Copyright (c) 2004, IC Plus Corp. 38/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet ROM MII Pin name Description (VLAN register 0) Default EEPROM registers 0EH E.4 --- E.3 -- -- E.2 -- -- E.1 -- -- E.0 -- -- Port0 VLAN look up table The register defines the ports in the same VLAN with port0. The bit 0~4 are corresponding to port 0~4. 1: port 4 and port0 are in the same VLAN 0: port 4 and port0 are not in the same VLAN Port0 VLAN look up table 1: port 3 and port0 are in the same VLAN 0: port 3 and port0 are not in the same VLAN Port0 VLAN look up table 1: port 2 and port0 are in the same VLAN 0: port 2 and port0 are not in the same VLAN Port0 VLAN look up table 1: port 1 and port0 are in the same VLAN 0: port 1 and port0 are not in the same VLAN Don't care 1'b1 1'b1 1'b1 1'b1 1'b1 ROM t4U.com MII Pin name Description (VLAN register 1) Default EEPROM registers 0FH F.7 --F.6 13.6 -- DataShee F.5 13.5 -- F.4 -- -- F.3 -- -- F.2 -- -- F.1 F.0 --- --- Don't care .com Port1 Class of service enable 1: enable, 0: disabled (default) Packets with high priority tag from port1 are handled as high priority packets. Port1 set to be high priority port 1: enable, 0: disabled (default) Packets received from port1 are handled as high priority packets. Port1 VLAN look up table The register defines the ports in the same VLAN with port1. The bit 8~12 are corresponding to port 0~4. 1: port 4 and port1 are in the same VLAN 0: port 4 and port1 are not in the same VLAN Port1 VLAN look up table 1: port 3 and port1 are in the same VLAN 0: port 3 and port1 are not in the same VLAN Port1 VLAN look up table 1: port 2 and port1 are in the same VLAN 0: port 2 and port1 are not in the same VLAN Don't care Port1 VLAN look up table 1: port 0 and port1 are in the same VLAN 0: port 0 and port1 are not in the same VLAN 1'b0 1'b0 1'b1 1'b1 1'b1 1'b1 .com Copyright (c) 2004, IC Plus Corp. 39/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet ROM MII Pin name Description (VLAN register 2) Default EEPROM registers 10H 10.7 --10.6 14.14 -- 10.5 14.13 -- 10.4 -- -- 10.3 -- -- t4U.com 10.2 10.1 --- --- 10.0 -- -- Don't care Port2 Class of service enable 1: enable, 0: disabled (default) Packets with high priority tag from port2 are handled as high priority packets. Port2 set to be high priority port 1: enable, 0: disabled (default) Packets received from port2 are handled as high priority packets. Port2 VLAN look up table The register defines the ports in the same VLAN with port2. The bit 0~4 are corresponding to port 0~4. 1: port 4 and port2 are in the same VLAN 0: port 4 and port2 are not in the same VLAN Port2 VLAN look up table 1: port 3 and port2 are in the same VLAN 0: port 3 and port2 are not in the same VLAN Don't care Port2 VLAN look up table 1: port 1 and port2 are in the same VLAN 0: port 1.com in the same VLAN and port2 are not Port2 VLAN look up table 1: port 0 and port2 are in the same VLAN 0: port 0 and port2 are not in the same VLAN 1'b0 1'b0 1'b1 1'b1 1'b1 DataShee 1'b1 ROM MII Pin name Description (VLAN register 3) Default EEPROM registers 11H 11.7 --11.6 14.6 -- 11.5 14.5 -- 11.4 -- -- 11.3 11.2 --- --- Don't care Port3 Class of service enable 1: enable, 0: disabled (default) Packets with high priority tag from port3 are handled as high priority packets. Port3 set to be high priority port 1: enable, 0: disabled (default) Packets received from port3 are handled as high priority packets. Port3 VLAN look up table The register defines the ports in the same VLAN with port3. The bit 8~12 are corresponding to port 0~4. 1: port 4 and port3 are in the same VLAN 0: port 4 and port3 are not in the same VLAN Don't care Port3 VLAN look up table 1: port 2 and port3 are in the same VLAN 0: port 2 and port3 are not in the same VLAN 40/57 1'b0 1'b0 1'b1 1'b1 .com Copyright (c) 2004, IC Plus Corp. July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet ROM MII Pin name Description (VLAN register 3) Default EEPROM registers 11H 11.1 --- 11.0 -- -- Port3 VLAN look up table 1: port 1 and port3 are in the same VLAN 0: port 1 and port3 are not in the same VLAN Port3 VLAN look up table 1: port 0 and port3 are in the same VLAN 0: port 0 and port3 are not in the same VLAN 1'b1 1'b1 ROM MII Pin name Description (VLAN register 4) Default EEPROM registers 12H 12.7 --12.6 15.14 -- 12.5 t4U.com 15.13 P4_high 12.4 12.3 --- --- 12.2 -- -- 12.1 -- -- 12.0 -- -- Don't care Port4 Class of service enable 1: enable, 0: disabled (default) Packets with high priority tag from port4 are handled as high priority packets. Port4 set to be high priority port 1: enable, 0: disabled (default) Packets received from port4 are handled as high priority packets. Don't care .com Port4 VLAN look up table The register defines the ports in the same VLAN with port4. The bit 0~4 are corresponding to port 0~4. 1: port 3 and port4 are in the same VLAN 0: port 3 and port4 are not in the same VLAN Port4 VLAN look up table 1: port 2 and port4 are in the same VLAN 0: port 2 and port4 are not in the same VLAN Port4 VLAN look up table 1: port 1 and port4 are in the same VLAN 0: port 1 and port4 are not in the same VLAN Port4 VLAN look up table 1: port 0 and port4 are in the same VLAN 0: port 0 and port4 are not in the same VLAN 1'b0 1'b0 DataShee 1'b1 1'b1 1'b1 1'b1 ROM MII Pin name EEPROM registers 13H 13[7:5] --13.4 -P4_FORCE Description Default Don't care Port4 force mode enable 1: enable force mode 0: disable force mode, port4 NWAY with all capability 0 .com Copyright (c) 2004, IC Plus Corp. 41/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet ROM MII Pin name EEPROM registers 13H 13.3 -P3_FORCE Description Default 13.2 -- P2_FORCE 13.1 -- P1_FORCE 13.0 -- P0_FORCE Port3 force mode enable 1: enable force mode 0: disable force mode, port3 NWAY with all capability Port2 force mode enable 1: enable force mode 0: disable force mode, port2 NWAY with all capability Port1 force mode enable 1: enable force mode 0: disable force mode, port1 NWAY with all capability Port0 force mode enable 1: enable force mode 0: disable force mode, port0 NWAY with all capability 0 0 0 0 ROM MII Pin name EEPROM registers 14H 14[7:5] --14.4 -P4_FORCE100 t4U.com Description Default 14.3 -- P3_FORCE100 14.2 -- P2_FORCE100 14.1 -- P1_FORCE100 14.0 -- P0_FORCE100 Don't care Force port4 to be 100M 1: force to be 100M 0: force to be 10M It is valid only if p4_force (13H[4]) is set to 1'b1. Force port3 to be 100M .com 1: force to be 100M 0: force to be 10M It is valid only if p3_force (13H[3]) is set to 1'b1. Force port2 to be 100M 1: force to be 100M 0: force to be 10M It is valid only if p2_force (13H[2]) is set to 1'b1. Force port1 to be 100M 1: force to be 100M 0: force to be 10M It is valid only if p1_force (13H[1]) is set to 1'b1. Force port0 to be 100M 1: force to be 100M 0: force to be 10M It is valid only if p0_force (13H[0]) is set to 1'b1. 0 DataShee 0 0 0 0 .com Copyright (c) 2004, IC Plus Corp. 42/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet ROM MII Pin name Description EEPROM registers 15H 15[7:5] --Don't care 15.4 -P4_FORCE_FULL Force port4 to be full duplex 1: force full duplex 0: force half duplex It is valid only if p4_force (13H[4]) is set to 1'b1. IP175A LF does not support "force 10M half mode". 15.3 -P3_FORCE_FULL Force port3 to be full duplex 1: force full duplex 0: force half duplex It is valid only if p4_force (13H[3]) is set to 1'b1. IP175A LF does not support "force 10M half mode". 15.2 -P2_FORCE_FULL Force port2 to be full duplex 1: force full duplex 0: force half duplex It is valid only if p4_force (13H[2]) is set to 1'b1. IP175A LF does not support "force 10M half mode". 15.1 -P1_FORCE_FULL Force port1 to be full duplex 1: force full duplex 0: force half duplex It is valid only if p4_force (13H[1]) is set to 1'b1. IP175A LF does not support "force 10M half mode". .com 15.0 -P0_FORCE_FULL Force port0 to be full duplex 1: force full duplex 0: force half duplex It is valid only if p4_force (13H[0]) is set to 1'b1. IP175A LF does not support "force 10M half mode". Default 0 0 0 0 t4U.com DataShee 0 ROM MII Pin name EEPROM registers 16H 16[4:0] 17[15:11] -- Description Default Add VLAN tag 16H[0] 1: port0 adds a VLAN tag to each outgoing packet. 0: port0 doesn't add a VLAN tag. 16H[1] 1: port1 adds a VLAN tag to each outgoing packet. 0: port1 doesn't add a VLAN tag. 16H[2] 1: port2 adds a VLAN tag to each outgoing packet. 0: port2 doesn't add a VLAN tag. 16H[3] 1: port3 adds a VLAN tag to each outgoing packet. 0: port3 doesn't add a VLAN tag. 16H[4] 1: port4 adds a VLAN tag to each outgoing packet. 0: port4 doesn't add a VLAN tag. 5'b0 .com Copyright (c) 2004, IC Plus Corp. 43/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet ROM MII Pin name EEPROM registers 17H 17[4:0] 17[10:6] -Description Default Remove VLAN tag 17H[0] 1: port0 removes the VLAN tag from each outgoing packet. 0: port0 doesn't remove the VLAN tag. 17H[1] 1: port1 removes the VLAN tag from each outgoing packet. 0: port1 doesn't remove the VLAN tag. 17H[2] 1: port2 removes the VLAN tag from each outgoing packet. 0: port2 doesn't remove the VLAN tag. 17H[3] 1: port3 removes the VLAN tag from each outgoing packet. 0: port3 doesn't remove the VLAN tag. 17H[4] 1: port4 removes the VLAN tag from each outgoing packet. 0: port4 doesn't remove the VLAN tag. 5'b0 t4U.com DataShee ROM MII Pin name EEPROM registers 18H~21H 18[7:0] 18[7:0] -- Description .com Default 19[7:0] 18[15:8] -- 1A[7:0] 19[7:0] -- 1B[7:0] 19[15:8] -- 1C[7:0] 1A[7:0] -- 1D[7:0] 1A[15:8] -- 1E[7:0] 1B[7:0] -- 1F[7:0] 1B[15:8] -- Vlan_tag_0_low This register defines the low byte of VLAN tag for port 0. (i.e. Port 0 vlan_tag[7:0]) Vlan_tag_0_high This register defines the high byte of VLAN tag for port 0. (i.e. Port 0 vlan_tag[15:8]) Vlan_tag_1_low This register defines the low byte of VLAN tag for port 1. (i.e. Port 1 vlan_tag[7:0]) Vlan_tag_1_high This register defines the high byte of VLAN tag for port 1. (i.e. Port 1 vlan_tag[15:8]) Vlan_tag_2_low This register defines the low byte of VLAN tag for port 2. (i.e. Port 2 vlan_tag[7:0]) Vlan_tag_2_high This register defines the high byte of VLAN tag for port 2. (i.e. Port 2 vlan_tag[15:8]) Vlan_tag_3_low This register defines the low byte of VLAN tag for port 3. (i.e. Port 3 vlan_tag[7:0]) Vlan_tag_3_high This register defines the high byte of VLAN tag for port 3. (i.e. Port 3 vlan_tag[15:8]) 44/57 8'b0 8'b0 8'b0 8'b0 8'b0 8'b0 8'b0 8'b0 .com Copyright (c) 2004, IC Plus Corp. July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet ROM MII Pin name EEPROM registers 18H~21H 20[7:0] 1C[7:0] -Description Default 21[7:0] 1C[15:8] -- Vlan_tag_4_low This register defines the low byte of VLAN tag for port 4. (i.e. Port 4 vlan_tag[7:0]) Vlan_tag_4_high This register defines the high byte of VLAN tag for port 4. (i.e. Port 4 vlan_tag[15:8]) 8'b0 8'b0 ROM MII Pin name Description (Testing & verify mode register 3) Default EEPROM registers 22H 22[7:6] --22[5:4] --22[3:0] --- Reserved Reserved Reserved 2'b01 2'b00 4'b0000 ROM t4U.com MII Pin name Description (Testing & verify mode register 4) Default EEPROM registers 23H 23[7:0] --- Reserved .com Description (Testing & verify mode register 5) 8'h00 DataShee ROM MII Pin name Default EEPROM registers 24H 24[7:0] --- Reserved 8'h01 .com Copyright (c) 2004, IC Plus Corp. 45/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet 4.12 Type R/W The basic MII registers Description Read/Write Type LL Description Latching Low SC RO Bit Function Self-Clearing Read Only R/W LH Latching High Description Default MII control register (address 00H) 15 Reset Not supported 14 Loop back R/W 13 Speed Selection RW t4U.com 12 Auto-Negotiation Enable RW 11 10 9 Power Down Isolate Restart AutoNegotiation R/W RW SC 8 Duplex mode R/W 7 6:0 Collision test Reserved R/W R/W 1 = Loopback mode 0 = normal operation When this bit set, IP175A LF will be isolated from the network media, that is, the assertion of TXEN at the MII will not transmit data on the network. All MII transmission data will be returned to MII receive data path in response to the assertion of TXEN. 1 = 100Mbps 0 = 10Mbps It is valid only if bit 0.12 is set to be 0. 1 = Auto-Negotiation Enable 0 = Auto-Negotiation Disable If port 4 is a fiber port, FXSD higher than 0.6v, this bit is fixed .com at 0. Not supported Not supported 1 = re-starting Auto-Negotiation 0 = Auto-Negotiation re-start complete Setting this bit to logic high will cause IP175A LF to restart an Auto-Negotiation cycle, but depending on the value of bit 0.12 (Auto-Negotiation Enable). If bit 0.12 is cleared then this bit has no effect, and it is Read Only. This bit is self-clearing after Auto-Negotiation process is completed. 1 = full duplex 0 = half duplex It is valid only if bit 0.12 is set to be 0. Not supported Write as 0, ignore on read 0 0 1 1 DataShee 0 0 0 0 0 - Bit Function R/W Description Default MII status register (address 01H) 15 100Base-T4 RO 1 = 100Base-T4 capable capable 0 = not 100Base-T4 capable IP175A LF does not support 100Base-T4. This bit is fixed to be 0. 0 .com Copyright (c) 2004, IC Plus Corp. 46/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet Bit Function R/W Description Default MII status register (address 01H) 14 100Base-X full RO 1 = 100Base-X full duplex capable duplex Capable 0 = not 100Base-X full duplex capable The default of this bit will change depend on the external setting of IP175A LF. If external pin setting without 100Base-X full duplex support, then this bit will change default to logic 0. 1 13 100Base-X half duplex Capable RO 12 10Base-T full duplex Capable RO 11 t4U.com 10Base-T half duplex Capable RO 10:7 Reserved 6 MF preamble Suppression 5 Auto-Negotiation Complete RO RO RO 4 Remote fault RO LH 3 Auto-Negotiation Ability RO 1 = 100Base-X half duplex capable 0 = not 100Base-X half duplex capable The default of this bit will change depend on the external setting of IP175A LF. If external pin setting without 100Base-X half duplex support, then this bit will change default to logic 0 1 = 10Base-T full duplex capable 0 = not 10Base-T full duplex capable The default of this bit will change depend on the external setting of IP175A LF. If external pin setting without 100Base-T full duplex support, then this bit will change default to logic 0 1 = 10Base-T half duplex capable 0 = not 10Base-T half duplex capable The default of this bit will change depend on the external setting of IP175A LF. If external pin setting without 100Base-X full duplex support, then this bit will change .com default to logic 0 Ignore on read 1 = preamble may be suppressed 0 = preamble always required 1 = Auto-Negotiation complete 0 = Auto-Negotiation in progress When read as logic 1, indicates that the Auto-Negotiation process has been completed, and the contents of register 4 and 5 are valid. When read as logic 0, indicates that the Auto-Negotiation process has not been completed, and the contents of register 4 and 5 are meaningless. If Auto-Negotiation is disabled (bit 0.12 set to logic 0), then this bit will always read as logic 0. 1 = remote fault detected 0 = not remote fault detected When read as logic 1, indicates that IP175A LF has detected a remote fault condition. This bit is set until remote fault condition gone and before reading the contents of the register. This bit is cleared after IP175A LF reset. 1 = Auto-Negotiation capable 0 = not Auto-Negotiation capable When read as logic 1, indicates that IP175A LF has the ability to perform Auto-Negotiation. The value of this bit will depend on the external mode setting of IP175A LF operation mode. 1 1 1 DataShee 1 0 0 1 .com Copyright (c) 2004, IC Plus Corp. 47/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet Bit Function R/W Description Default MII status register (address 01H) 2 Link Status RO 1 = Link Pass LL 0 = Link Fail When read as logic 1, indicates that IP175A LF has determined a valid link has been established. When read as logic 0, indicates the link is not valid. This bit is cleared until a valid link has been established and before reading the contents of this registers. 0 1 Jabber Detect 0 Extended capability RO 1 = jabber condition detected 0 = no jabber condition detected When read as logic 1, indicates that IP175A LF has detected a jabber condition. This bit is always 0 for 100Mbps operation and is cleared after IP113A reset. This bit is set until jabber condition is cleared and reading the contents of the register. 1 = Extended register capabilities 0 = No extended register capabilities IP175A LF has extended register capabilities. 0 1 t4U.com Bit Function R/W Description Default PHY Identifier (address 02H) 15:0 PHY identifier RO DataShee IP175A .com LF OUI (Organizationally Unique Identifier) ID, the 0243h msb is 3rd bit of IP175A LF OUI ID, and the lsb is 18th bit of IP175A LF OUI ID. IP175A LF OUI is 0090C3. Bit Function R/W Description Default PHY Identifier (address 03H) 15:10 PHY identifier RO 9:4 3:0 Manufacture's Model Number Revision Number RO RO IP175A LF OUI ID, the msb is 19th bit of IP175A LF OUI ID, and lsb is 24th bit of IP175A LF OUI ID. IP175A LF model number IP175A LF revision number 3h 05h 0 Bit Function R/W Description Default Auto-Negotiation Advertisement register (address 04H) 15 Next Page Not supported 14 Reserved RW Reserved by IEEE, write as 0, ignore on read 13 Remote Fault 12:11 Reserved 10 Pause 9 .com 100BASE-T4 R/W Not supported RO Reserved for future IEEE use, write as 0, ignore on read RW 1 = Advertises that this device has implemented pause function 0 = No pause function supported RW Not supported 0 0 0 0 0 0 48/57 Copyright (c) 2004, IC Plus Corp. July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet Bit Function R/W Description Default Auto-Negotiation Advertisement register (address 04H) 8 100BASE-TX full R/W 1 = 100BASE-TX full duplex is supported duplex 0 = 100BASE-TX full duplex is not supported 7 100BASE-TX R/W 1 = 100BASE-TX is supported 0 = 100BASE-TX is not supported 1 1 6 5 4:0 10BASE-T full duplex R/W 10BASE-T Selector Field 1 = 10BASE-T full duplex is supported 1 0 = 10BASE-T full duplex is not supported R/W 1 = 10BASE-T is supported 1 0 = 10BASE-T is not supported R/W Use to identify the type of message being sent by 00001 Auto-Negotiation. Bit Function R/W Description Default Link partner ability register (address 05H) Base Page 15 Next Page RO 1 = Next Page ability is supported by link partner 0 = Next Page ability does not supported by link partner 0 14 t4U.com Acknowledge Remote Fault RO RO 13 12:11 Reserved 10 Pause RO RO 9 8 7 6 5 4:0 100BASE-T4 100BASE-TX full duplex 100BASE-TX 10BASE-T duplex 10BASE-T Selector Field full RO RO RO RO RO RO 1 = Link partner has received the ability data word 0 0 = Not acknowledge 0 1 = Link partner indicates a remote fault 0 = No remote fault indicate by link partner .com If this bit is set to logic 1, then bit 1.4 (Remote fault) will set to logic 1. Reserved by IEEE for future use, write as 0, read as 0. 0 1 1 = Link partner support IEEE802.3x 0 = Link partner does not support IEEE802.3x IP175A LF will reload the default value after rest or link failure. 1 = Link partner support 100BASE-T4 0 0 = Link partner does not support 100BASE-T4 1 = Link partner support 100BASE-TX full duplex 0 0 = Link partner does not support 100BASE-TX full duplex 1 = Link partner support 100BASE-TX 0 0 = Link partner does not support 100BASE-TX 1 = Link partner support 10BASE-T full duplex 0 0 = Link partner does not support 10BASE-T full duplex 1 = Link partner support 10BASE-T 0 0 = Link partner does not support 10BASE-T Protocol selector of the link partner 00000 DataShee .com Copyright (c) 2004, IC Plus Corp. 49/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet 5 5.1 Electrical Characteristics Absolute Maximum Rating Stresses exceed those values listed under Absolute Maximum Ratings may cause permanent damage to the device. Functional performance and device reliability are not guaranteed under these conditions. All voltages are specified with respect to GND. Supply Voltage Input Voltage Output Voltage Storage Temperature Ambient Operating Temperature (Ta) -0.3V to 4.0V -0.3V to 5.0V -0.3V to 5.0V -65C to 150C 0C to 70C 5.2 DC Characteristic Sym. VCC VCC_IO VCC_IO Tj Min. 2.0 3.1 3.3 0 Typ. 2.15 Max. 2.625 3.5 3.5 125 Unit V V V Conditions Operating Conditions Parameter Supply Voltage Supply Voltage Supply Voltage Operation Junction Temperature Power Consumption Input Clock Parameter Frequency Frequency Tolerance I/O Electrical Characteristics Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Sym. VIL VIH VOL VOH Min. Typ. Max. 0.8 Unit V V V V Conditions Sym. Min. Typ. 25 Max. Unit MHz PPM Conditions Pin 120 REG_OUT is not used. Pin 120 REG_OUT is used. 70 t4U.com DataShee 1.485 .com W VCC=2.25v -50 +50 2.0 0.4 2.4 IOH=4mA, VCC_IO_x=3.3V IOL=4mA, VCC_IO_x=3.3V .com Copyright (c) 2004, IC Plus Corp. 50/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet 5.3 5.3.1 AC Timing Reset Timing Description Min. Typ. Max. Unit X1 valid period before reset released Reset period MII clock comes out period after reset released Power on VCC OSCI (X1) X1 valid period before reset released 10 10 - 1 - ms ms s Reset released resetb Reset period MII clock MII clock comes out period after reset released t4U.com DataShee .com 5.3.2 MII0 PHY Mode Timing a. Transmit Timing Requirements Symbol Description Min. Typ. Max. Unit TTxClk TTxClk TsTxClk ThTxClk Transmit clock period 100M MII Transmit clock period 10M MII TXEN0, TXD0 to MII0_TXCLK setup time TXEN0, TXD0 to MII0_TXCLK hold time T T xC lk 2 0.5 40 400 - - ns ns ns ns M II0 _T X C L K T hT xC lk T X E N 0, T X D 0 [3:0] T sT xC lk .com Copyright (c) 2004, IC Plus Corp. 51/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet b. Receive Timing Symbol Description Min. Typ. Max. Unit TRxClk TRxClk TdRxClk Receive clock period 100M MII Receive clock period 10M MII MII0_RXCLK falling edge to RXDV0, RXD0 TRxClk 1 40 400 - 4 ns ns ns MII0_RXCLK TdRxClk RXDV0, RXD0[3:0] t4U.com DataShee .com .com Copyright (c) 2004, IC Plus Corp. 52/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet 5.3.3 MII1 PHY Mode Timing a. Transmit Timing Requirements Symbol Description Min. Typ. Max. Unit TTxClk TTxClk TsTxClk ThTxClk Transmit clock period 100M MII Transmit clock period 10M MII TXEN, TXD to MII1_TXCLK setup time TXEN, TXD to MII1_TXCLK hold time T T xC lk 2 0.5 40 400 - - ns ns ns ns M II1 _T X C L K T hT xC lk T X E N 1, T X D 1 [3:0] T sT xC lk t4U.com b. Receive Timing Symbol .com Description DataShee Min. Typ. Max. Unit TRxClk TRxClk TdRxClk Receive clock period 100M MII Receive clock period 10M MII MII1_RXCLK falling edge to RXDV1, RXD1 TRxClk 1 40 400 - 4 ns ns ns MII1_RXCLK TdRxClk RXDV1, RXD1[3:0] .com Copyright (c) 2004, IC Plus Corp. 53/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet 5.3.4 MII0 MAC Mode Timing a. Receive Timing Requirements Description Min. Typ. Max. Unit Symbol TRxClk TRxClk TsRxClk ThRxClk Receive clock period 100M MII Receive clock period 10M MII RXDV, RXD to MII_RXCLK setup time RXDV, RXD to MII_RXCLK hold time 2 0.5 40 400 - - ns ns ns ns T R xC lk M II_ R X C L K T hR xC lk R X D V , R X D [3:0 ] T sR xC lk t4U.com b. Transmit Timing .com Description DataShee Symbol Min. Typ. Max. Unit TTxClk TTxClk TdTxClk Transmit clock period 100M MII Transmit clock period 10M MII MII_TXCLK rising edge to TXEN, TXD TTxClk MII_TXCLK TdTxClk TXEN, TXD[3:0] 1 40 400 - 4 ns ns ns .com Copyright (c) 2004, IC Plus Corp. 54/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet 5.3.5 SMI Timing a. MDC0/MDIO0 Timing Description Min. Typ. Max. Unit Symbol Tch Tcl Tcm Tmd Tmh Tms MDC0 High Time MDC0 Low Time MDC0 period MDIO0 output delay MDIO0 setup time MDIO0 hold time 40 40 80 10 10 - 5 - ns ns ns ns ns ns MDC0 T ms T mh M D IO 0 W r ite C yc le t4U.com MDC0 T cl T cm DataShee .com T ch T md M D IO 0 R e a d C yc le .com Copyright (c) 2004, IC Plus Corp. 55/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet 5.3.6 EEPROM Timing a. Symbol Description Min. Typ. Max. Unit TSCL TsSCL ThSCL Receive clock period SDA to SCL setup time SDA to SCL hold time T SCL SCL T hS C L SDA T sSCL 2 0.5 20480 - - ns ns ns R ead data cycle b. t4U.com DataShee Symbol TSCL TdSCL Description Transmit clock period .com Min. Typ. Max. Unit SCL falling edge to SDA - 20480 - 5200 ns ns TSCL SCL TdSCL SDA Comand cycle 6 Order Information Part No. IP175A IP175A LF Package 128-PIN QFP 128-PIN QFP Notice Lead free .com Copyright (c) 2004, IC Plus Corp. 56/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com www..com IP175A LF Preliminary Data Sheet 7 Package Detail HD D 128 103 128 PQFP Outline Dimensions 1 102 38 65 39 64 t4U.com e b GAGE PLANE A1 A2 .com c HE E Symbol A1 A2 b c HD D HE E e L L1 y Dimensions In Inches Min. Nom. Max. 0.010 0.014 0.018 0.107 0.112 0.117 0.007 0.009 0.011 0.004 0.006 0.008 0.669 0.677 0.685 0.547 0.551 0.555 0.906 0.913 0.921 0.783 0.787 0.791 0.020 0.025 0.035 0.041 0.063 0.004 0 12 Dimensions In mm Min. Nom. Max. 0.25 0.35 0.45 2.73 2.85 2.97 0.17 0.22 0.27 0.09 0.15 0.20 17.00 17.20 17.40 13.90 14.00 14.10 23.00 23.20 23.40 19.90 20.00 20.10 0.50 0.65 0.88 1.03 1.60 0.10 0 12 D L1 L y Note: 1. Dimension D & E do not include mold protrusion. 2. Dimension B does not include dambar protrusion. Total in excess of the B dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. IC Plus Corp. Headquarters 10F, No.47, Lane 2, Kwang-Fu Road, Sec. 2, Hsin-Chu City, Taiwan 300, R.O.C. TEL : 886-3-575-0275 FAX : 886-3-575-0475 Website: www.icplus.com.tw .com Copyright (c) 2004, IC Plus Corp. Sales Office 4F, No. 106, Hsin-Tai-Wu Road, Sec.1, Hsi-Chih, Taipei Hsien, Taiwan 221, R.O.C. TEL : 886-2-2696-1669 FAX : 886-2-2696-2220 57/57 July 12, 2005 IP175A LF-DS-R07 DataSheet 4 U .com |
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